Dual in-line memory modules (DIMMs) have long been a popular form of digital memory for computing systems due to their high availability and adherence to form factor and electrical interface standards. Typically, a DIMM employs multiple memory devices, such as dynamic random access memories (DRAMs), residing on a single, small printed circuit board (PCB) to provide a large amount of memory to a processing system, such as a desktop computer, a network server, or other similar computing system. On DIMMs, memory devices are populated on both faces of the PCB, while single in-line memory modules (SIMMs) contain memory devices on only one side of the PCB. Oftentimes, the memory devices are logically organized into one or more “ranks,” or separately addressable areas of memory. Further, each memory device associated with a particular rank contains a specific range of bits of each addressable location of the memory; thus, the bit width of each addressable location is normally directly related to the number of memory devices employed in the rank.
Each DIMM is typically coupled to a memory controller on a processing system motherboard by way of a connector so that the DIMM may be easily replaced in the event the DIMM becomes defective. Replacement may also occur in order to upgrade the capacity or speed of the DIMM. Typically, the motherboard provides several DIMM connectors to allow a range of memory capacities to present the customer a choice in price-performance tradeoffs.
As the speed and performance capabilities of processors used within computing platforms have continued to increase, commensurate enhancements in memory technology have created significant implementation issues. For example, increased memory capacities of DIMMs require more input/output (I/O) signals, such as address and data signals, between each DIMM and the motherboard, worsening a preexisting I/O signal routing problem. Also, higher DIMM access speeds have decreased the number of DIMMs that may be coupled to a memory controller due to the transmission line “stubs” created on the address and data signal lines between the controller and the DIMMs.
To address these problems, fully-buffered dual in-line memory modules (FB-DIMMs) have been devised. Each FB-DIMM includes a number of memory devices, such as DRAMs, plus an advanced memory buffer (AMB) for coupling the DRAMs with the memory controller. Instead of coupling the memory controller directly with each of the DIMMs, the memory controller is coupled by way of two unidirectional serial command and data interfaces with a first of the DIMMs. That DIMM is coupled with the next DIMM in a similar fashion, resulting in a point-to-point serial interface connecting the controller and DIMMs in a chain-like fashion. As a result, the use of the serial interfaces simultaneously resolves the signal routing problem and the transmission line maladies of prior DIMMs. Thus, more DIMMs may be coupled with any one memory controller, thus facilitating significant increases in memory capacity while also allowing faster memory access times.
However, FB-DIMM technology does not address the growing problem of increased DRAM failure rates associated with the DRAM speed and capacity advances mentioned above. To deal with this issue, memory controllers driving traditional DIMM systems and more recent FB-DIMM systems employ redundancy data, such as error correction codes (ECC) or cyclic redundancy check (CRC) codes, stored within one or more extra DRAMs of a DIMM to correct data errors. While some of these errors are transient or temporary in nature, others may be indicative of a failing DRAM. To address a defective DRAM, the memory controller may use one of the extra DRAMs of both traditional DIMMs and FB-DIMMs as a spare so that the memory controller may map the contents of a failing DRAM to the spare DRAM, thus removing the failing DRAM from service without requiring replacement of the DIMM. However, with DRAM failure rates continuing to increase, one spare DRAM per DIMM may not be enough to allow replacement of the DIMM before a second DRAM fails, thus causing a complete failure of the DIMM. Further, even if two or more spare DRAMs are provided, current memory controllers typically are not equipped to utilize those spares effectively. In addition, when employing an extra DRAM as a spare, the error correction capability of the memory controller is reduced, since less storage is available for the error correction data as a result.